Xichao

I like working at both ends of the stack: designing hardware in SystemVerilog, and building the tooling that makes machine learning systems measurably better. Right now I'm writing a RISC-V CPU for my computer architecture course and benchmarking LLM judges that grade robot training data.

Before that I built web apps and Discord bots in Python and TypeScript, which is how I got into programming.

• GitHub

Projects

• Robot subtask judge evaluation

  Benchmarks a vision-language LLM judge that flags bad subtask annotations on Unitree G1 teleoperation data. It scores the judge against 856 human-labelled segments (precision, recall, F0.5) and tunes the judge prompt by hand and with GEPA.

• Instruction Architectures & Compilers labs

  SystemVerilog hardware simulated with Verilator and tested with C++ testbenches, built toward a RISC-V CPU. It includes scripts that set up and check the full toolchain.

• JournalApp

  A full-stack journaling app with a Django backend and a React + TypeScript frontend, documented in a LaTeX write-up.

• jambot

  A Discord bot written in Python with discord.py, one of my first projects.